1. Field of the Invention
This invention relates to bipolar unity gain buffers and, more specifically, to such a buffer capable of operation with reduced power consumption relative to prior art bipolar unity gain buffers.
2. Brief Description of the Prior Art
Testing of higher pin count and higher bandwidth integrated circuit logic devices requires a much higher circuit density and power dissipation per unit area than ever previously considered. To increase circuit density, the super small outline package (SSOP) can be used. The power dissipation of this SSOP is much less than the small outline intergrated circuit (SOIC) and plastic leaded chip carrier (PLCC) packages used presently by the automated test equipment (ATE) industry. Innovative changes must be made to improve bandwidth and reduce power dissipation in the ATE pin electronics.
The pin electronics comprises a 3-stateable driver, a dual comparator or receiver and a 3-stateable load. The driver must be capable of driving a series terminated 50 ohm transmission line up to 5 and 8 volt amplitudes at a rate of 5 volts/nanosecond. For the typical A/B class complementary bipolar driver output stage to drive these high amplitudes, the bias current of the output buffer must be increased. The output stage already provides a significant portion of the power dissipation for this device. New circuit designs are therefore required to reduce the power dissipation of the driver output stage and to improve the bandwidth in the same design.
Commercially available bipolar monolithic driver integrated circuits generally use an A/B class output stage. In many prior art drivers, this output stage is a standard A/B complementary bipolar unity gain buffer. In one prior art device, an A/B unity gain buffer is provided having an output stage which senses the output current wherein supplemental current is provided to the output transistor base nodes when a fixed output current is exceeded. This supplemental current is increased after the output current requirement is sensed. This feedback method causes glitches or a stair stepped effect during large voltage swing transients. For an operational amplifier booster, the circuit is adequate. However, for an ATE driver, edge placement accuracy and linear edge speed is required. A glitch or stair stepped effect during the transient could false trigger or double clock a logic device being stimulated during test. It is therefore apparent that an improved buffer and specifically an improved unity gain buffer is highly desirable.